1. Technical Field
The present invention relates generally to a method of manufacturing integrated circuit (IC) chips and the IC chips formed by the implementation of the method. More specifically, the present invention relates to methods to prevent divot formation in shallow trench isolation areas.
2. Background Art
The trend in semiconductor device fabrication towards increasing density of circuit components requires that smaller areas of the circuit be devoted to isolation of the circuit components and capacitative storage devices. The need to reduce the surface area used for circuit components such as isolation structures and large area capacitor devices has resulted in the development of structures vertically oriented with respect to the plane of the substrate surface. These vertical structures typically consist of some type of trench structure sunk into the semiconductor substrate and are positioned between charge carrying components of adjacent transistors. The utilization of a trench structure enables the formation of a structure having large volume while minimizing the amount of surface area consumed.
However, the formation of vertically oriented isolation structures does not completely eliminate the possibility of current leakage paths. Accordingly, various isolation techniques have been developed and are used in advanced integrated circuitry to electrically isolate the various devices in the semiconductor substrate. One technique, shallow trench isolation, is often used in IC chips to provide higher device densities and better planarity than other isolation methods.
In this technique, the shallow trench isolation area is first defined to form isolation trenches surrounded by areas of wafer having a pad oxide layer and a polish-stop nitride layer on the surface. The isolation trench is then thermally oxidized to form a thin oxide layer on the isolation trench surfaces. A thin nitride liner is often deposited inside the isolation trench surfaces to prevent stress during the subsequent oxidation steps because the stress causes dislocations in the silicon wafer. The isolation trench is then filled with a chemical vapor deposited ("CVD") oxide and chemically mechanically polished ("CMP") back to the polish-stop nitride layer to form a planar surface. The polish-stop nitride layer is then removed. At this time, if there is a nitride liner, exposed areas of the nitride liner are etched back as well, creating a divot. If there is no nitride liner, a divot can still form in the SiO.sub.2 surface adjacent to the Si due to stress at the Si--SiO.sub.2 interface. The pad oxide is then removed by a wet etch, which may also cause the divot to grow. The gate oxide is then grown on the silicon wafer surface and the gate polysilicon ("gate poly") is deposited. When the gate poly is deposited, it will fill the divots, causing an enhanced electric field or corner device, which may affect the threshold voltage of the field effect transistor ("FET").
In order to solve this problem, methods have been suggested e.g., one by Fazan et al., IEDM, 1993, p. 57 in which an oxide spacer is formed after the polish stop nitride is removed. However, problems still occur when using the oxide spacer because there is no etch stop and it is possible to damage the underlying silicon wafer during the reactive ion etch ("RIE") process used to form the oxide spacer. Additionally, if the oxide spacer is too thin, it may be completely removed during the subsequent wet etches and divots may form.
Accordingly, a need exists for a method to reduce the likelihood of the formation of divots in order to reduce the number of chips that fail. Furthermore, the method should be relatively simple and performed using existing tools.